1. Field of the Invention
The present invention relates to a process for fabricating multilayer composite structures that integrate electronic, optoelectronic, and/or power components and functionalities.
2. Background of the Related Art
Many unsuccessful attempts have been made to find satisfactory methods for producing structures integrating electronic metal oxide semiconductor (MOS) layers and electronic, optoelectronic, and/or power components of the III-V semiconductor type. The production of such structures integrating electronic components on a single platform requires combining single-crystal silicon layers of high crystalline quality, for producing MOS layers such as complementary metal oxide semiconductors (CMOS) circuits, with III-V semiconductor type materials (such as GaAs, InP and other similar alloys) to form electronic, optoelectronic and/or power components.
The direct epitaxial growth of III-V semiconductor materials on silicon by chemical vapor deposition (CVD) techniques and molecular beam epitaxy (MBE) techniques has been studied over recent decades without obtaining good results in terms of crystalline quality. These techniques have encountered problems of emergent dislocations, antiphase domains, and point defects, among others.
According to another known technique, it is possible to physically transfer thin single-crystal films of InP or GaAs material onto a silicon substrate without significantly impairing the intrinsic crystalline quality of these films. This technique is described in an article by E. Jalaguier et al. titled Transfer of 3 in GaAs Film on Silicon Substrate by Proton Implantation Process, published in Electronics Letters, Feb. 19, 1998, Vol. 34, No. 4, pp. 408-409. This film transfer is carried out using the well-known Smart-Cut™ technology, an example of which is described in U.S. Pat. No. 5,374,564 and in an article by A. J. Auberton-Hervé et al. titled Why Can Smart-Cut Change the Future of Microelectronics?, published in the International Journal of High-Speed Electronics and Systems, Vol. 10, No. 1, 2000, pp. 131-146.
Furthermore, it has been demonstrated that it is possible to combine the growth techniques with film transfer techniques in order to integrate silicon and III-V materials on the same mechanical platform.
According to a first method of implementation, one way of obtaining GaAs on a 200 mm diameter silicon wafer, without having a GaAs donor substrate, consists in growing GaAs on a single-crystal germanium (Ge) substrate. Growing GaAs on germanium makes it possible to obtain very high-quality thin films owing to the very small lattice parameter mismatch between these two materials. However, because of the cost and mechanical fragility of these bulk substrates, it is more advantageous to transfer a thin germanium film on silicon (such as GaAs and InP) and then carry out crystalline growth of GaAs. The GaAs thus obtained has a quality equivalent to GaAs grown epitaxially on a bulk GaAs substrate.
GeOI structure (germanium on silicon with an intermediate insulating film) has been demonstrated on large diameters (up to 200 mm). To date, this is the most direct methodology for combining silicon and GaAs.
However, for the integration of microelectronic, optoelectronic and/or power functions on silicon and III-V materials, this structure has several drawbacks. With an epitaxially grown GaAs/Ge transferred structure, it is difficult to produce CMOS components on the silicon support substrate because it is necessary to first locally expose the silicon in order to fabricate the circuit thereon. In addition to the problem of specific thermal budget during the fabrication, the topology makes it difficult, or even impossible for the circuit to be electrically connected to the optical component.
According to a second method of implementing this technique, structures with a silicon active layer for the surface CMOS components and an optically active layer beneath the silicon layer have thus been developed for overcoming these drawbacks.
U.S. Pat. No. 6,645,829 and U.S. Pat. No. 6,677,655 describe the fabrication of structures that include buried active optical layers, such as a [Si substrate/oxide (SiO2)/Ge layer/Si layer] or else a [Si substrate/oxide (SiO2)/Si layer/Ge layer/oxide (SiO2)/Si layer].
However, in structures of this type, the optically active layer is always in direct contact with a silicon layer of higher or lesser quality depending on the method of fabrication (epitaxy or bonding) used for producing the silicon layer.
Moreover, U.S. Patent Application Publication No. 2004/0252931 discloses forming multilayer structures by bonding a multilayer monolithic electronic device, which includes an electrically active layer and an optically active layer, to another layer, the electrical and optical layers possibly being silicon on insulator (SOI) layers transferred onto a support substrate.